Field of the Invention
The present invention relates to a quasi-vertical semiconductor component having at least two inner cells disposed in a well, a buried layer provided between the well and a semiconductor substrate, and a sinker zone (“terminal zone” for the buried layer), which connects the buried layer to a surface of the semiconductor component.
A quasi-vertical semiconductor component of this type is described for example in the reference by B. Murari et al., titled “Smart Power ICs”, Springer, pages 20 and 32 to 36.
The basic construction of a conventional quasi-vertical semiconductor component of this type is illustrated in a sectional illustration in FIG. 5. The semiconductor component may be, by way of example, a diode, a vertical DMOS transistor, a bipolar transistor or a thyristor.
In all these cases, the quasi-vertical semiconductor component has, for example, a p-conducting semiconductor substrate 1 made of silicon and an n-conducting semiconductor layer 2 likewise made of silicon, for example, provided on the substrate 1. In this case, the semiconductor layer 2 can be applied to the semiconductor substrate 1 by epitaxy.
Situated between the semiconductor substrate 1 and the semiconductor layer 2 is an n+-conducting buried layer 3, which is connected via a likewise n+-conducting sinker zone 4 to a surface of the semiconductor component at which an n++-conducting terminal zone 5 with a sinker terminal 6 is provided. In general, for the sinker zone 4 it is possible to use any type of conducting connection between the buried layer 3 and the surface, such as, for example, a trench filled with doped polycrystalline silicon.
With the buried layer 3 and the sinker zone 4, which is configured in an annular fashion, if appropriate, a common n-conducting well 7 is formed in the semiconductor layer 2, the well 7 containing various inner cells 8 which are connected in parallel with one another via a common terminal 9.
An edge termination 10 provides for a dielectric strength between the last inner cell 8 and the sinker zone 4 that does not form a limitation for the component.
The edge termination 10 may contain a suitable combination of diffusions in the well 7, an insulation layer containing, for example, silicon dioxide and/or silicon nitride and a field plate (e.g. made of metal or polysilicon) lying above the insulation layer.
Depending on the type or construction of the inner cells 8, the quasi-vertical semiconductor component illustrated is a diode, a vertical DMOS transistor, a bipolar transistor or a thyristor.
It should be noted at this point that the conductivity types specified here and below are only examples. It is thus possible, of course, to provide the conductivity types in opposite fashion, that is to say, by way of example, to replace the n conductivity type with the p conductivity type and vice-versa. Equally, it is possible to use any suitable semiconductor material such as, in particular, silicon, silicon carbide, etc. for the quasi-vertical semiconductor component.
FIG. 6 shows, as a first concrete example for the semiconductor component of FIG. 5, the construction of a quasi-vertical up-drain DMOS transistor, that is to say of a DMOS transistor whose drain terminal does not lie on the rear side of the substrate as in the case of a vertical structure, but rather on the same side as a gate terminal and a source terminal or a body terminal. In this case, the inner cells 8 contain a p-conducting body zone 11 and an n-conducting source zone 12, it being possible to provide the body zone 11 and the source zone 12 with a common contact 13.
The individual source zones 12 of the various inner cells 8 may be produced by diffusion and run parallel to drain from sinker zone 4, buried layer 3 and well 7. However a polygonal configuration of the respective inner cells 8 is also possible.
Situated between the individual source zones 12 are gate electrodes 14 on a non-illustrated gate oxide.
The current from the source zones 12 flows via the channels formed beneath the gate electrodes 14 in the body zones 11 into the common well 7 and from the latter to the buried layer 3, from where the current flows further via the sinker zone 4 and the terminal zone 5 into the sinker terminal 6 forming a drain terminal.
If, in the example of FIG. 6, the gate electrodes 14 are omitted and the terminals for the body zones 11 and the source zones 12 are led out separately, then a bipolar transistor is produced, as is illustrated in FIG. 7, where it has a common p-conducting base zone 15 with p+-conducting base terminal zones 16 and also n-conducting emitter zones 17 embedded in the base zone 15. The base zones 16 and the emitter zones 17 in the common well 7 are respectively connected together in this case. The sinker terminal 6 forms a collector terminal in the bipolar transistor.
FIG. 8 shows, in a simplified illustration, an impedance network which corresponds to the examples of FIGS. 5 to 7 and reveals how the buried layer 3 causes a voltage drop on account of its internal resistance with resistances R1, R2, R3, . . . between the individual inner cells 8. Moreover, if appropriate there may be a gradient in the RC constant of the respective body-drain diodes of the individual inner cells 8 from outside, that is to say from the sinker zone 4 inward to the cell. This gradient in the RC constant, that is to say in the admittance Y (R, C)=1/Z (Z=impedance) is illustrated diagrammatically by the individual imaginary resistances in FIG. 8. In the case of a high current density or rapid voltage changes, it becomes apparent to a greater extent, the more inner cells 8 lie parallel to one another in the well 7 and the higher the resistance of or the lower the doping of the buried layer 3.
In the case of a quasi-vertical semiconductor component of the type outlined above, what are critical are primarily operating points for which the power loss is high and in which the current i at a common terminal 18 is greatly dependent on the voltage u present at the sinker terminal 6.
It is, then, typically the case for reverse-biased or avalanche operation of all types of quasi-vertical semiconductor components that in the latter the sinker voltage u in the case of a specific avalanche or reverse current i2 abruptly falls or “snaps back” to a low voltage. This is also referred to as “snap-back”. The snap-back is undesirable for many semiconductor components and limits their safe operating area. For other semiconductor components, such as ESD protection structures (ESD=ElectroStatic Discharge), for example, the snap-back is desirable, which usually holds true only in the event of optimum utilization of the available area.
It is desirable in both cases above, however, for the power loss to be distributed uniformly over the area of the inner cells 8 in the well 7 and for all the inner cells 8 to trigger to their “avalanche characteristic curve” under an identical or at least similar operating point.
FIG. 9A, which illustrates the forward current i1 of a semiconductor component having inner cells 1 to N as a function of the sinker voltage u, and FIG. 9B, which shows the dependence of the reverse current i2 of the semiconductor component as a function of the sinker voltage u of the semiconductor component, then reveal that the individual inner cells 8 (the cell 1 designates a cell located the nearest to the sinker zone 4, while the zone N/2 indicates a cell in the center of the well 7), have very different operating points, the position of these operating points depending on the distance between the respective inner cells 8 and the sinker zone 4. In this case, the first cell (cell 1), which reaches its trigger current with respect to a snap-back (in this respect, see especially FIG. 9B), limits the strength of the semiconductor component overall.
A further cause of why a gradient in the current yield of the individual inner cells 8 lying parallel to one another may be undesirable could possibly lie in the complex scalability of the current properties of the semiconductor component with the number of inner cells thereof, which in turn results from the voltage drop in the buried layer 3.
Therefore, a fundamental problem in quasi-vertical semiconductor components is that the operating points of the inner cells are greatly dependent on the sinker voltage u and the inner cells are therefore at different operating points depending on their distance from the sinker zone 4. This results in a non-optimum utilization of the available semiconductor area in cases of a high power loss such as at the breakdown of the semiconductor component.